FPGA modeling techniques for detecting and demodulating multiple wireless protocols

In an increasingly interconnected world, the rising number of wireless devices in the Internet of Things has caused heavy congestion on particular bandwidths (BWs). Due to spectrum scarcity, the need has arisen for these devices to operate on the same BWs. However, existing wireless devices are inflexible and have no capabilities to coexist with devices using other protocols. In this work, we propose new FPGA-based design techniques to receive multiple protocols on the same computing platform. Our methods incorporate tunable parameters, such as FIR filter length and number of bits per fixed-point word, to explore design tradeoffs regarding clock cycle, resource utilization, power consumption, and detection accuracy. We separate the physical (PHY) layer receive chains into a set of building blocks, including rate transition, pattern detection, and OFDM demodulation. We investigate implementation of the LTE physical downlink shared channel (PDSCH) and 802.11a protocols to test our techniques. LTE is the standard for high-speed wireless communication for mobile phones and data terminals; Wi-Fi uses variants of IEEE 802.11a. To ease the system development process, we develop our models using MathWorks Simulink, which supports auto-generation of HDL code for the non-critical sections and incorporation of hand-tuned HDL code as part of its black box interface. Our building blocks can be used by the wireless system modeling community to meet the needs of modern evolving wireless standards. In the future, our framework will allow researchers to achieve high-performance transceiver implementations on FPGA fabric for multiple cutting edge protocols.