Speed-up of high accuracy analog test stimulus optimization

Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. Firstly, a review of the state of the art is presented. Then, the algorithm is introduced and the methodology of our approach is described. Finally, results on CMOS 2-stage op amp and conclusions are given.