Optimized face detection on FPGA

This paper gives the hardware implementation of face detection on FPGA using Haar features. The design consisting of integral image generation which is used to compute the Haar features at a faster rate, has been illustrated. The classifiers are built using the AdaBoost algorithm which selects a minimum number of critical Haar features from a very large set. Also, parallel processing classifiers increase the speed of the face detection system by rejecting non-faces quickly. The described detection architecture has been designed using Verilog HDL and implemented on Xilinx vertex-5 FPGA which shows optimization in terms of area and speed.