Technique for generating timing skew resistant time-interleaved signals

A technique generating timing skew resistant time-interleaved signals is proposed. With a simple logic function, all the timing alignment critical signals' falling edges or rising edges can be trimmed by the master clock without introducing charge injection. Thus the generated time-interleaved signals are resistant to timing skew. When these time-interleaved signals are applied to a time-interleaved ADC, the extra complex technique for timing skew calibration can be saved.