Error free sense amplifier circuit design for STT-MRAM nonvolatile memory

The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPU's. The most capable NVM component is STT-MRAM, which enhances the performance by 3.3 nS access time. It has strong radiation hardness, higher integrity and maximum endurance compared to SRAM. The power consumption of STT-MRAM is decreased by an order of magnitude by reducing the writing current. In this article, a new error free sense amplifier circuit is proposed. The detail analysis of the sense amplifier circuit is provided here. Finally, the performance of the proposed the sense amplifier is compared with existing sense amplifiers.