Area efficient soft error tolerant RISC pipeline: Leveraging data encoding and inherent ALU redundancy

This paper proposes novel soft error detection and mitigation technique in reduced instruction set computer (RISC) based pipeline processors. We leveraged the data encoding techniques (re-computing with rotated operands (RERO)) in conjunction with back pressure controlling mechanism in pipeline architecture. In order to alleviate the performance degradation due to potential stalling, we exploited the inherent ALU redundancy in conjunction with data encoding. Synthesis results on Stratix II FPGA from Altera suggested that if 5% of the instructions are subject to soft error then for 2.25 additional stall cycles (on average) our proposed ALU-redundancy based solution in conjunction with data encoding provides better execution time even if the clock cycle time increases up to 11% because of additional hardware. Area wise our technique requires up to 3 times lesser area compared to other contemporary techniques and provides soft error tolerance in combinational blocks along with intermediate registers.