An adaptive edge decision feedback equalizer with 4PAM signalling

This paper presents an adaptive edge decision feedback equalizer (DFE) with 4PAM signaling. Optimal DFE tap coefficients and threshold voltages for data recovery are obtained adaptively using sign-sign least-mean-square (SS-LMS) algorithms that minimize data jitter. Clock and data recovery is carried out using a dual phase/frequency-locked loop. A 10 Gbps 4PAM serial link has been designed in a 65 nm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 models. Simulation results demonstrate that the proposed adaptive edge DFE is capable of opening completely closed data eyes at the far end of a backplane channel with -25 dB boud-rate attenuation with 46.5% and 56% horizontal and vertical eye-openings, respectively while consuming 66 mW power.