Low-power low-noise amplifier IIP3 improvement under consideration of the cascode stage

This paper presents a linearity analysis to give insights into the impact of the cascode stage in a common-source low-noise amplifier (LNA) that is designed with subthreshold biasing and a linearity enhancement technique. It is shown how the third-order intermodulation intercept point (IIP3) of the subthreshold LNA improves through addition of an inductor and a digitally programmable capacitor at the gate of the cascode transistor. A 1.8 GHz LNA was fabricated in 0.11μm CMOS technology to demonstrate the linearization approach with chip measurements. The linearized low-power LNA has a 14.8 dB voltage gain, a 3.7 dB noise figure, and a -3.7 dBm IIP3 with a power consumption of 0.336 mW.