Multi-standard low-power DDR I/O circuit design in 7nm CMOS process

This paper presents novel circuit techniques to implement DDR I/O circuit design that can support multiple low-power standards in a state-of-art 7nm CMOS finfet process. Hybrid pull-up driver with a power gating switch is proposed to support a wide range of data rates and output swing levels. The usage of both thin and thick gate oxide devices in the final output stage effectively achieves minimal power consumption while enabling 6.4Gbps/pin data rate. The proposed input receiver directly converts the incoming signal's common mode levels to the optimal level of the 1st stage amplifier by a replica feedback loop. Frequency peaking technique is also employed to suppress the inter-symbol interference (ISI) and increase overall bandwidth of the receiver. Simulation results are provided.