900-MHz, 3.5-mW, 8-bit pipelined subranging ADC combining flash ADC and TDC

The time-based ADC (TB-ADC) is gaining attention as a key technology to solve challenges concerning CMOS scaling; however, it cannot achieve high speeds and a high resolution at the same time. We proposed a TB-ADC architecture combining a flash ADC and TDC to achieve both high speeds and a high resolution. The flash ADC and the ADC using a VTC and TDC are pipelined to enhance the conversion speed. The charge steering amplifier is used for the low-power residue transfer. Moreover, the Vernier TDC using the dynamic delayer enables low-power operation. An 8-bit ADC test chip fabricated using 65-nm CMOS technology demonstrated a high sampling frequency of 900 MHz and a low-power consumption of 3.5 mW. The FOM was 32 fJ/conv.-step.