DDR4 dual-contact interconnect methodology, component, and board level reliability

This article is a series of study on new generation of electronic contact challenges and component interconnects technology for high-end computing products. These products include server and data storage for cloud computing applications at the data center as well as core routers for service providers, edge and branch routers for enterprise networking companies, and small switch and wireless router for commercial and small and home office. All these cloud computing products require high data speed in terabytes per second and high signal integrity for the massive mobile users and loT application whenever and wherever they connected To achieve such mobility and signal integrity the major focus is the electrical interconnections between the CPUlGPU and component in the system. Due to the large number of edge-card connections such as DIMM, PCle, etc. in modern computer systems and due to their relatively low reliability, in previous Part 2 of the study a test vehicle with daisy chain was used to assess the contact interconnect failure related to factors such as soldering flux residue, plating quality, contact interface cleaning and doubt insertion, and particulate control and management. As concluded in Part 2, the heavy flux residue and vibration preconditioning have medium effect on contact failure, however contact interface cleaning and particulate control show no significant contribution and not able to eliminate the last thousands DPPM of DIMM contact failure. The purpose of current study is to look into a new generation of dual-contact interconnect methodology and assess component level contact configuration and interconnect reliability. First, the contact pin configuration and plating morphology such as homogeneity and thickness are carefully examined to ensure contact integrity between DDR4 connect and DIMM module can be achieved. Then normal force of dual-pin and individual first and second contact were measured to benchmark to existing conventional single-contacts. Furthermore the JEDEC Raptor test vehicle was adapted to assess characteristic impedance and four signal integrity tests, RL (return loss), IL (insertion loss), NEXT (near-end cross talk), and FEXT (far-end cross talk) to ensure signal integrity requirements are fulfilled. Finally, board level reliability test is proposed for Raptor test board and trial run on real product. The overall goal of Part 3 of the study is to ensure a smooth migration from conventional single-contact to a new interconnect mechanism with robust board and system reliability for high signal integrity requirement in cloud computing and loT application.