Chip-package co-design for optimization of 5.8GHz CMOS LNA performance

The co-design of chip-package is imperative for low noise amplifier (LNA) to achieve the best circuit performance. This paper describes a LNA matching network design by using external surface mount technology (SMT) elements on land grid array (LGA) package, and proposes simulation-based co-optimization methodologies that achieve power gain over than 10dB at 5.8GHz. The design scheme shows that the off-chip matching network is an efficient alternative to on-chip matching for low fabrication cost because of less silicon area and low cost LGA package.