An effective functional safety infrastructure for system-on-chips

With increasing use of electronic systems in vehicles for managing critical functionality, the requirements for safety in automotive chip architectures are becoming mandatory. Thus, automotive chips must provide functional safety capabilities in addition to the general functionality. Augmenting logic and memory BIST (Built-in Self-Test) solutions with new features is one of the options to facilitate safety at chip level. The augmented solution self-test the logic and memory at power-up/power-down and during mission mode to ensure that the chip is fault-free or react if it is faulty. In this paper, an effective infrastructure is presented which allow detection of faults for functional safety.