NBTI/PBTI tolerant arbiter PUF circuits

In this paper, we propose NBTI/PBTI (negative/positive bias temperature instability) tolerant arbiter PUF (physical unclonable function) circuits and evaluate its performance. The PUF is a technology for generating cryptographic keys and authenticating by utilizing physical characteristics, such as electronic delays, built in the devices when they were manufactured. It can perform encryption and authentication without directly holding the key, and has resistance to various eavesdropping attacks. On the other hand, its function may change due to aging degradation. To overcome this problem, we propose three types of NBTI/PBTI tolerant arbiter PUF circuits. These circuits cut off the stress voltage when it is in the standby mode. In the first type of circuit, cutoff features are added to all MOS transistors. In the second type of circuit, cutoff features are added to the MOS transistors which have a large influence on the delay. In the third type of the circuit, cutoff feature is added only to the primary input. Experiment by the SPICE simulation is carried out in order to evaluate our proposed circuits. The results show that there is a tradeoff between cost and error reduction rate, and the error rate is reduced to 1/8 in the best case.