Test mode power computation and IR drop analysis of application specific integrated circuits implementing face detection algorithms

The switching activity due to various test vectors has direct effect on amount of power consumption during testing. Due to higher switching activity during test mode compared to the switching activity during functional mode the power consumption may be higher than functional mode power consumption. The excessive average and instantaneous power requirement during slow speed and high speed test conditions may results in test failure and test escapes due to higher IR drop affecting the yield and the quality of the design. It is necessary to study the switching activity, power consumption and IR drop during various test conditions. The objective is to compute test mode power, establish correlation between computed and silicon power consumption data and to analyze IR drop during various test conditions. This study using 32nm design used for implementing face detection algorithm should provide insight into test mode power issues on chips implementing Face detection algorithms and help controlling the overall test environment more efficiently to minimize the power usage and the IR drop.