Design of an active power pulsation buffer using an equivalent series-resonant impedance model

In single-phase power converters, passive power pulsation decoupling buffers (capacitors or LC circuits) have been widely adopted to reduce the twice-line frequency voltage and current ripple. With constant demands for higher power density and efficiency, active implementations of power pulsation buffers have always been an attractive prospect. While various implementations of active buffers have been studied in literature, this paper proposes a general method to identify and analyze dc side active buffers by using an equivalent impedance model of a traditional passive solution. This impedance model provides insight into the circuit and control design of such active buffers. To illustrate this impedance model, the series-stacked buffer (SSB) architecture is identified as a shunt resonant impedance at the twice-line frequency. A control scheme with converter loss compensation capability is developed and generalized to both voltage and current control architectures. The model and associated control architecture is verified with a 1.5 kW, 400 V SSB hardware prototype.