A design method of decoupling circuits for a digital PCB to reduce high frequency current on power and ground planes

This paper describes a design technique of decoupling circuits that can reduce high frequency current rushing into the power/ground planes of a digital PCB. In this technique, the IC is modeled as a current source of high frequency, and a parameter that represents the effect of the high frequency current reduction is derived. Then, by using the parameter, a design procedure to obtain the optimal bypass capacitor and the decoupling inductor is shown. Furthermore, validity of this modeling is shown by experimental study.