Two-step monotonic switching scheme for low-power SAR ADCs

In this paper the simple method to reduce the switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register (SAR) analog-to-digital converters (ADCs) is described. The method is based on the well-known monotonic switching procedure and the use of one intermediate voltage level during switching. Unlike most recently published switching methods the proposed method does not require the intermediate voltage to be accurate. The implementation of digital control and an intermediate voltage-level generator is considered. To evaluate the reduction in switching energy compared to the conventional monotonic switching procedure, the behavioral model of a 10-bit ADC was examined. The additional digital logic, voltage generator, and capacitive DAC were modeled at the transistor level using a 65 nm STM design kit. Simulation results and the subsequent power efficiency gains are presented.