A 0.5 V low-voltage low-dropout regulator

This work proposes a low-dropout (LDO) regulator to provide low supply voltage of 0.5 V with the input range from 0.7 V to 0.9 V. The reference voltage of this LDO regulator is generated with the zero temperature coefficient circuit composed by MOS transistors in the subthreshold condition. And the error amplifier utilizes the constant gate-source potential mirrored biasing techniques to cope with the wide variation in supply voltage before regulation. The 0.5 V output voltage is boosted with varying the bulk potential of the transistor to obtain the optimal performance between light load and heavy load with maximum output current of 50 mA. Fabricated with a CMOS 0.18-μm technology, this LDO regulator occupies the area of 633μm×630μm including pads. And the active area is 0.097 mm².