Co-Simulation and modelling for heterogeneous integration of high-tech electronic systems

This paper details the current status and future requirements of modelling and simulation tools in supporting chip, package, and board level co-design for advanced packaging (3D-IC's with TSV's, WLP, SiP, etc.) of heterogeneous integrated systems. These tools will drive innovations across the die-package-system domains by optimizing electrical, thermal, mechanical and reliability performance for a diverse range of high-technology systems such as mobile devices, IoT, data centers, power conversion to name a few. At present, the chip, package and board (system) communities tend to undertake design and analysis separately. For highly integrated heterogeneous systems this approach must change. This is particularly important as, for example, chip-package interactions are now becoming a major performance and reliability risk.