Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package

In recent years, the IoT popularity pushes the package development of 3C products into a more functional and thinner target. For high I/O density and low cost considered package, the promising Fan-out Wafer Level Packaging (FOWLP) provides a solution to match OSAT existing capability, besides, the chip last process in FOWLP can further enhance the total yield by selectable known-good dies (KGDs). However, under processing, the large portion of molding compound induces high warpage to challenge fabrication limitation. The additional leveling process is usually applied to lower the warpage that caused by the mismatch of coefficient of thermal expansion and Young's modulus from carriers, dies, and molding compound. This process results in the increase of package cost and even induce internal damages that affect device reliability. In order to avoid leveling process and improve warpage trend, in this paper, we simulated several models with different design of molding compound and dies, and then developed a multi-chip last FOWLP test vehicle by package dimension of 12x15 mm2 with 8x9 and 4x9 mm2 multiple dies, respectively. The test vehicle performed three redistribution layers (RDLs) including one fine pitch RDL of line width/line spacing 2um/2um, which is also the advantage of multi-chip last FOWLP, and also exhibited ball on trace structure for another low cost option. For the wafer warpage discussion, the results showed that tuning the thickness of molding compound can improve warpage trend, especially in the application of high modulus carrier, which improved wafer warpage within 1mm, for package warpage discussion, the thinner die can lower the warpage of package. Through well warpage controlling, the multi-chip last FOWLP package with ball on trace design was successfully presented in this paper, and also passed the package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uHAST 96 hrs, and drop test by board level reliability.