Advances in Wire Bonding Technology for 3D Die Stacking and Fan Out Wafer Level Package

Vertical stacking semiconductor devices can effectively integrate more functionality in the same footprint. Memory devices are often stacked in 8 and 16 die, and prototypes for up to 64 die have had proven concepts. For many of these devices, wire bonding on unsupported die edge in overhang configurations is required. Controlling the impact force, bonding parameters and lift off force profile are all critical to achieve robust wire bonding results and prevent pad and die crack. FEA models are developed to study the wire bonding process on overhang die configurations and understand impact of influential factors such as die thickness, overhang distance, substrate, die attach material and bonding temperature. Adaptive learning software (K&S patent pending) has been developed to calibrate the compliance at each bond pad and automatically optimize bonding parameters per bond site. Wire bonding processes on challenging overhang devices are developed using this new optimization software. Results show improvements in the bonding capability and bonding speed, and reduction in die crack. The recent development in Fan-out Wafer Level Packaging (FOWLP) lowers package cost, achieves thinner packages with higher electrical performance. Recently developed Fan Out-based package-on-packages increase the interconnect density for the interface between the vertically stacked fan out logic device and wire bonded memory device. A new Vertical Wire process has been developed to provide a higher density through mold interconnect (TMI) for vertically stacked FOWLP. The process flow for this new packaging innovation is presented in the paper with cost comparison to other TMI methods such as electroplated Cu pillar. Bonding results are presented with analysis of wire height variation and location accuracy for as bonded condition and after molding and back-grinding for various diameter Cu wires from 18um to 63um which show the capability of the process.