Development of a Multi-project Fan-Out Wafer Level Packaging Platform

Fan-Out Wafer Level Packaging (FOWLP) is one of the latest trends in microelectronics packaging. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, low thermal resistance, high RF performance due to shorter interconnects together, as the direct IC connection by thin film metallization instead of wire bonds or flip chip bumps yields low parasitic effects. Especially inductance of FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also integrate embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications. FOWLP is in volume manufacturing since a couple of years and services are offered in Asia as well as in Europe. But especially for low volume quantities and prototyping no dedicated packaging services are available. Adapting the success story of Si-based Multi-Project Wafer technology that offers fast and cost-effective access to low numbers of chips, Multi-Project Fan-out Wafer Level Packaging might be an option to address heterogeneous integration for the prototyping market. Within this study such a Multi-Project Fan-out Wafer Level Package (MPFOWLP) technology has been developed and evaluated with focus on RF applications. To demonstrate an entire prototyping run Si dies from a Multi-Project Wafer were used. For technology evaluation six different chips have been selected where five of them were functional dies for application frequencies up to 120 GHz. Additionally one dedicated test die was used, allowing on the one hand RF characterization of the technology approach and on the other hand interconnect testing and reliability characterization. A uniform package size of 10 × 10 mm² was chosen and design rules for the redistribution layer (RDL) have been fixed at the beginning. A two metal layer design and a BGA pin-out have been chosen allowing also the integration of antenna structures in the RDL. Based on these boundary conditions package designs have been done. Reticle and fan-out wafer design were integrated on a 200 mm reconfigured wafer. Based on this approach around 38 packages of each type come out of one wafer. Packaging technology followed the RDL last approach, where dies are first embedded into mold compound forming a reconfigured wafer and subsequently a thin film redistribution layer is applied to the reconfigured wafer. Final process steps are solder ball placement and package singulation by dicing. In summary this paper describes the development and evaluation run of a Multi-Project Fan-out Wafer Level Package approach for RF application.