Soft error evaluation for InGaAs and Ge complementary FinFETs

With relentless scaling of transistor dimensions, the single cell soft error rate (SER) reduces with each technology node [1]. InGaAs and Ge complementary FinFET technology is promising for next generation NMOS/PMOS FETs, due to their superior transport properties [2] over silicon, but their soft error performance is unexplored to date. Previous work investigated the SER in InAs nFinFET assuming symmetrical NMOS and PMOS current and exposed the vulnerability of InAs FinFET compared with Si FinFET [3]. In this work, we evaluate the soft error rates in InGaAs n-channel and Ge p-channel FinFETs for complementary logic application.