A low-Power PGA with DC-Offset Cancellation in 65 nm CMOS process

A low-Power Programming Gain Amplifier (PGA) with DC-Offset Cancellation for long term evolution (LTE) is implemented in a 65-nm CMOS. The proposed PGA is composed of a three-stage sub-VGA with DC-offset cancellations (DCOC) and common-mode feedbacks (CMFB). The gain of the proposed PGA ranges from 0 dB to 42 dB with a step of 3 dB, which can be easily tuned by switched-resistors and switched-capacities. The proposed VGA achieves a tunable gain up to up to 6 dB by the first stage, up to 12 dB by the second stage, and up to 24 dB by the third stage respectively. The DCOC is adapted to cancel the DC offset voltage introduced by the mismatch presented in circuits. At the same time, CMFB is utilized to reduce the mismatch between the top and bottom current sources. It has a low power consumption of 2.76 mW at a supply of 1.2 V with 10 MHz's gain bandwidth (GBW), input-referred noise of 18 nV/vHz.