A background calibration technology for capacitance mismatch in pipelined ADCs with 2.5-bit/stage MDAC

In traditional pipelined ADCs, errors originated by capacitance mismatch, finite amplifier gain, incomplete settling and offset. To overcome capacitance mismatch for >=2.5-bit/stage MDAC architecture, a new background digital calibration strategy is proposed in this paper. Based on this technique, a 14-bit, 40MS/s pipelined ADC is implemented. The simulation results show that ENOB is improved from 9.7 bits to 13.3 bits with σ=0.5% capacitance mismatch within 1s. The chip is fabricated in 0.18um CMOS process, occupied an active area of 4×4mm2, including on-chip decouple capacitors, with 110mW power consumption at 3.3 V.