A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with simplified power-efficient digital control logic

This paper presents a 7.9 fJ/conversion-step 10-bit 125 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) on the basis of a monotonic capacitor switching procedure. Simplified power-efficient digital control logic, multi-layer sandwich capacitor structure and high-speed level-shift bootstrapped sampling-and-holding (S/H) blocks are employed to achieve high performance with low power consumption. The prototype is implemented in 55 nm standard CMOS process, occupying an active area of 0.18 mm × 0.20 mm. Post simulation results show that an SNDR of 54.01 dB and an ENOB of 8.7 bit can be achieved by consuming 0.41 mW of the ADC core from a 1.2 V supply, and a figure of merit (FOM) of 7.9 fJ/conversion-step.