An ultra-low power Dual-Ring factorial Delay Locked Loop in 28nm FD-SOI technology

This paper introduces a technique for balancing input and output timing of factorial ring owing to achieving higher accuracy as well as reduction of counter delay and reference spurs. Besides, this design offers an 8-bit programmable counter for a more flexible frequency synthesizer. The initial objective was for generating a 2.5GHz signal. However, thanks to the wide tuning range of the Voltage Controlled Delay Elements (VCDEs), the system has output performance spreads from 1 to 3.5GHz. On full system simulation, the power consumption is approximately 150uW with power supply of 1V. The system was implemented on 28nm FD-SOI with verifications by full-system simulations at transistor level.