Design of a parametric-drift-resistant inverter

As a basic logic unit of integrated circuit, the stability of parameters of inverter have a direct effect on the performance of system. This paper starts from parametric drift of traditional inverter caused by the variation of threshold voltage of MOSFET. Then a new parametric drift-resistant inverter is proposed. This structure utilizes compensation circuit to solve parametric drift such as the decrease of low level noise margin and the high voltage of output, the drift of transfer characteristic curve. Finally, Cadence is utilized to verify the validity of this inverter and this structure is generalized to NAND gate to solve its parametric drift.