The analysis of ESD degradation in p-type poly-Si thin film transistor

Electrostatic discharge (ESD) effect in the p-type polycrystalline thin film transistor (poly-Si TFT) are investigated by employing a transmission line pulses with different durations (100ns and 200ns). The experimental results shown that P+/poly-Si junction governs the transition of the off-state phase and on-state phase observed in the TLP I-V curves. In addition, the breakdown mechanism in the poly-Si TFT is a thermal process and then the breakdown voltage decreases with the increment of pulse width. By considering of electron trapping in the gate oxide and creation of defect states in the Si/SiO₂ interface, evolutions of threshold voltage, hole field effect mobility and sub-threshold swing relevant to ESD latent damage are also presented.