DSP-RAM: A logic-enhanced memory architecture for communication signal processing

In this paper a new parallel computational RAM (C/spl middot/RAM) architecture, called DSP-RAM, is proposed to speed up a class of digital signal processing (DSP) algorithms in telecommunications. The proposed architecture integrates memory and single instruction stream, multiple data stream (SIMD) parallel processing into a single chip. Key elements of the architecture were designed to verify their cost in silicon area. A software simulator was written in C++ to evaluate the performance of DSP-RAM implementations of critical components in the ITU G.728 voice coding standard.