A supposedly clever thing i'll never do again

“An expert is a person who has found out by his own painful experience all the mistakes that one can make in a very narrow field.”1 If one learns more from regrets than from successes, then there is knowledge to be gained from this paper. Upon reflecting on the designs of five different time interleaved ADCs over the past decade many mistakes were made. Some of the most clever ideas turned out not to fulfil all their potential. This paper will focus primarily on the use of a slow, but accurate, reference ADC for system-identification approaches for background calibration in time-interleaved ADCs. Although still a valid approach, the complications are varied, multi-dimensional, convoluted and ultimately limits performance in a variety of unanticipated ways. Specific issues that arise include: cross-talk from sub-sampled clocking of the reference ADC, environmental changes due to different power supply conditions during calibration than exists in normal operation, sub-sampled kickback that does not appear uniformly on every sample and slice dependent kickback as each slice cannot be routed an identical distance from the reference ADC. These issues will be discussed in the context of two specific time-interleaved ADCs, an 8b 6-GS/s circuit in 90nm CMOS and a 12b 2.7GS/s in 130nm BiCMOS.