Low-power CMOS receivers for short reach optical communication

Emerging applications for short-reach optical communication require low-power receiver circuits in nanoscale CMOS technologies. An analysis of optical receivers with broadband input transimpedance reveals that their power consumption increases rapidly as bit-rate increases. This has motivated work on bandwidth-limited optical receiver front-ends. For example, receivers employing decision feedback equalization (DFE) and correlated-double sampling (CDS) are analyzed, showing that they significantly relax the bandwidth requirements of the analog front-ends, permitting their low-power implementation in CMOS. Finally the design of an optical receiver utilizing an integrate-anddump (ID) front-end is described. The receiver is implemented in 28nm CMOS and achieves -8.3dBm sensitivity at 20Gbps consuming 0.7pJ/b.