Design and analysis of linear feedback shift register(LFSR) using gate diffusion input(GDI) technique

In chip manufacturing technology, reduction in chip size possess great concern for power dissipation. Low power testing has become an important issue as power dissipation during testing mode is very high as compare to normal mode. LFSR is used in testing of ASIC chips by generating pseudo random patterns. This paper deals with design of low power LFSR by using GDI technique. GDI technique is one of the low power technique used for implementing various digital circuits. This technique uses only two transistors to design fast and low power circuits with improvement in power characteristics. LFSR has been implemented by conventional and GDI technique in Cadence Virtuoso at 90nm technology. Comparative analysis is carried out between the two methods showing upto 45.4% and 20% reduction in power and area respectively in GDI technique. Simulation and variation of power with frequency and voltage is also discussed.