2-dimensional minimum fast-searching design approach of LDPC decoder architecture for IEEE 802.11n/ac/ax applications

This work proposes a systematic design approach to perform minimum and second minimum fast-searching in 2-dimensional xy-planes. This fast-searching approach can extremely improve the calculating timing in LDPC decoder architecture, especially for high row weights defined in IEEE 802.11n/ac/ax SPEC. In a design example with row weight of 22, our developed approach only requires about 42.9% of critical-path timing under 12.2% hardware overhead with respect to often-used binary-tree approach. This approach also extends to other various high row weights for enhancing critical-path timing performance.