A SIMD-based software fault tolerance for ARM processors

This paper develops a SIMD-based software fault tolerance technique for ARM processors. The core technique employs instruction-level redundant execution to tolerate bit-flipping errors. The proposed approach is implemented in the LLVM compiler to generate reliable code automatically. For the tested benchmark programs, preliminary experiments show that the proposed approach can correctly generate fault-tolerant codes at costs of 4.7%-70.2% performance degradation on average compared with the original versions. The fault-tolerant versions of code are 1.44-2.54 times larger than the original versions.