Effect of wafer bias frequency on microtrenching during high selective gate etching

We have studied the effect of wafer bias frequency on etch selectivity degradation at the feature periphery. Experiments were performed on an ECR plasma etcher which had an ECR plasma source and independent wafer biasing system. Several bias frequencies between 13.56 MHz and 400 kHz with pulsed ECR plasma were used to examine the effect on occurrence of pitting of the underlying oxide, which is called microtrenching. In this experiment, we found that the lower the bias frequency became, the less microtrenches were observed, even in the case of a bias power condition which had the same selectivity in sparse areas. These results imply that lowering the bias frequency can efficiently suppress topography dependent variation of selectivity. Furthermore, by using a sub-MHz bias frequency under low power conditions, we have achieved microtrenching-free gate etching against 2.5 nm-thick gate oxide.