Charge-up damage of dual gate transistor during RF pre-cleaning of metal contact before barrier metal deposition

The damage of dual gate (p-gate PMOS and n-gate NMOS) transistors during RF pre-cleaning of their metal contacts before barrier metal deposition has been investigated in logic devices by varying the aspect ratio of metal contacts and RF source power. With higher aspect ratios and a higher source power for RF pre-cleaning, the gate leakage current of PMOS increases, while that of NMOS stays constant. We present a possible explanation for this difference in damage behaviour.