A New High Performance VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic

A new high-performance VLSI architecture for least mean square (LMS) adaptive filter using distributed arithmetic (DA) is presented. It is based on storing possible filter partial products in a look-up table (LUT) followed by a shift accumulation (SA) unit. Usually, all the address location of LUT need to be re-calculated in every iteration. In this paper, we proposed a new strategy for updating the LUT contents without rotation of addresses in successive iterations. This results in a low complexity implementation with high speed. The proposed technique employs random-access memory (RAM) based LUT for storing offset binary coding (OBC) combinations of input samples and filter weights. The savings achieved are significant due to less routing complexity for large order filter. Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) synthesis shows that the proposed design occupies lesser area and consumes lesser power and provides higher throughput as compared to existing schemes. For example, a 32 - taps adaptive filter with the proposed technique occupies almost 20 % less area and achieves 12.63 % clock speedup for 2 - taps sub-filter as compared to the best existing scheme.