System generator model-based FPGA design optimization and hardware co-simulation for Lorenz chaotic generator

Chaotic systems can be synchronized and used for secure communication to transmit video, audio and text files. Field Programmable Gate Arrays (FPGAs) are beneficial for the implementation of high speed, low cost and low power embedded communication systems. In this paper, a model-based design approach is presented for FPGA implementation and optimization of chaotic generators. Lorenz attractor has its significance in studying chaotic systems and is used as the design subject in this paper. The conceptual model design is built using MATLAB Simulink, and the equivalent hardware model is created using Xilinx System Generator for FPGA implementation. The design models are created with 32-bit fixed-point and 16-bit fixed-point data formats and implemented on FPGA to evaluate the design performance, including the maximum operating clock frequency, resource utilization and power consumption. The 32-bit and 16-bit fixed-point models are further optimized by using timing analysis and adding delays to break critical paths to improve timing performance. The implementation results show that the proposed design and optimization approach has achieved promising improvement on design performance by tripling the maximum operating frequency for both 32-bit and 16-bit fixed-point configurations. The FPGA hardware co-simulation results demonstrate the anticipated Lorenz chaotic generator outputs for both designs.