A qaud_byte implementation of 8B10B decoder in JESD204B protocol

JESD204B is the newest industry standard used as the high-speed interconnection between data converter and digital signal processor, which supports serial data transfer rate up to 12.5 Gbps. According to the function requirements for 8B10B decoder in JESD204B protocol, a quad_byte parallel processing method is proposed which can reduce operating frequency of decoding circuit significantly thus result in an easier implementation in low-cost CMOS technology library. Simultaneously, it uses the polarity information to simplify the decoding table thus reduce the circuit area, uses the state control to improve the precision of polarity detection, and uses the parallel topological structure to accelerate the circuit speed. Circuit simulation and synthesization results show that our design has certain advantages at operating frequency and circuit area compared with other typical implementation, fully meeting the requirements of JESD204B protocol.