Methodology for automated and recursive verification of verilog-AMS models against schematic

In this paper, a Verilog-AMS based methodology for automated verification is discussed. This solution is geared towards aiding the verification of behavioral models, which designers are tasked with when developing or editing a schematic. Up to now the conventional way to verify the operation of a model and how much it mimics the operation of a schematic is to visually inspect the output signals between models and schematics. The proposed methodology compares the signals and outputs a digital bit, indicating if the difference between schematic and model falls within the user defined tolerance range. The solution also prints a pass/fail error messages into a log file which can be easily reviewed by the designer. As a result a more accurate and user friendly platform is presented for verification, saving a significant amount time during the top level verification phase of a project.