Design and FPGA implementation of DDS based on waveform compression and Taylor series

Direct Digital Frequency Synthesis (DDS) or Numerically Controlled Oscillators (NCO) is an important functional blocks in digital communication systems. DDS is widely used in the fields of radar, communication and electronic warfare. It plays an important role in digital up-conversion, down-conversion, demodulation of phase and frequency. This paper brings out the FPGA implementation of one such DDS which has quadrature outputs. The proposed design, which is based on look-up table (LUT) using wave compression and Taylor series calculation, has considerable improvement in terms of spurious free dynamic range (SFDR) compared to other existing designs based on traditional LUT. The design is implemented on Xilinx Zynq XC7Z020-1CLG484 FPGA, fabricated in 28 nm process technology. The design has utilized 489 slice flip flops and 388 4-input LUTs as its hardware count. The SFDR of proposed DDS is 114 dBc, which has improved by 70dB than traditional DDS.