Design optimization of board-level signal integrity depending on PCB stack-up configuration in a mobile device

In this paper, a board-level signal integrity design depending on printed circuit board (PCB) stack-up configuration is presented. The design object is an embedded Multi-Chip Package (eMCP) interface which is employed for low-cost and high-performance memory interface in low-or mid-tier mobile devices. The eMCP interface is fabricated on a PCB with a 2-6-2 layer stack-up and staggered micro-via process. For signal integrity optimization, an eMCP interface design based on a double signal-layer stack-up is proposed. For validation of the proposed design, characteristic impedance, crosstalk, and eye-diagram simulation were conducted using a 3-dimentional field solver and the results were compared with those of the previous single signal-layer design. With the validation results, it has been successfully demonstrated that the proposed design achieved noticeable improvement on the impedance matching, crosstalk reduction, and eye-opening.