FPGA implementation of different NRZ line coding schemes

The paper presents the FPGA implementation of the line coding scheme Non Return to Zero (NRZ). The NRZ line encoder and decoder are implemented in Verilog using MentorGraphics ModelSim Edition 10.4a. The three encoding schemes namely NRZ-Level, NRZ-Mark and NRZ-Space are implemented. The algorithms for the encoder and decoder are functionally verified and are made synthesizable using Xilinx V.10. The performance of the synthesized hardware is studied for different FPGAs families and devices such as Spartan 3E, Virtex 4 and Virtex 5. A performance comparison in the terms of utilized logic, power and delay is presented. The analysis of the results shows preference for Virtex 5 FPGAs in high speed data transmission whereas the Spartan 3E FPGA can be utilized in low power data transmission.