Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer (T_FE) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of T_FE on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing TFE yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as T_FE is increased. Depending on the attributes of the underlying transistor, increasing T_FE beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of T_FE on the circuit energy-delay. Our analysis shows that for high T_FE, the delay of the circuit may increase with an increase in supply voltage. However, for voltages <;0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay.