Enhancing yield learning on SoC designs by tracking IP manufacturability

To enhance System on a Chip (SoC) yield this paper proposes understanding IP contributions. Data structures specific to IP design characteristics for test manufacturing data system can support this goal. This data provides a knowledge foundation and connects the knowledge traditionally siloed into Design, Fab and Test areas. Such a knowledge enhances the ability to comprehend manufacturability at the IP level. Metrics specific to IP blocks are proposed. This paper concludes with potential benefits for manufacturing engineers.