Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications

The increasing industrial demand for low data-rate and low power networking protocols for IoT communications from past several years led to the development of ZigBee technology. As a result of advancement in VLSI technologies, development of more power efficient, accurate, and small digital ZigBee transmitter design has become achievable but yet challenging. This paper presents digital design and FPGA PoC implementation for the 2.4 GHz-band digital ZigBee transmitter. The proposed hardware design of the transmitter described by utilizing Verilog Hardware Description Language and the prototype implementation is done by employing Xilinx Vivado 2016.2. The paper demonstrates the design of the four building blocks of an energy efficient digital ZigBee transmitter; i.e. cyclic redundancy check, bit-to-symbol block, symbol-to-chip block, and offset quadrature phase shift keying Modulator. Simulation waveform verifies functionality of the transmitter and its low power and low data-rate suitability for Internet of Things' applications.