Defect generation in Si substrates during plasma processing: Model prediction and characterization techniques

The increasing demand for higher performance of ULSI circuits requires aggressive shrinkage of device feature sizes in accordance with Moore's law. Plasma processing plays an important role in achieving fine patterns with anisotropic features in metal-oxide-semiconductor field-effect transistors (MOSFETs). Despite advancements in plasma processing, the degradation of material properties due to plasma exposure has become a key issue. Such degradation mechanisms - the negative aspect of plasma processing - are usually referred to as “plasma-induced damage” [1, 2]. In general, plasma-induced damage (PID) is categorized into three types on the basis of the mechanism of its generation [2], namely, “charging damage”, “radiation damage”, and “physical damage”. Charging damage [3] is induced by conduction current from plasma flowing into dielectric materials in MOSFETs, while radiation damage is caused by high-energy photon interactions in materials [4]. Physical damage is induced by high-energy ion bombardment on Si substrates or other material surfaces. The ion bombardment damage forms the surface modified region and creates localized defect structures underneath the region. Recently the created defects in Si substrates have been considered to be a cause of the so-called Si recess [5, 6] and the performance degradation of MOSFETs [7-9]. One of the critical concerns regarding this plasma-induced physical damage (PPD) is the fact that the damage generation mechanism is governed by basic plasma parameters, in other words, the damage does not naturally scale with the device feature sizes. This paper provides an overview of the modeling and characterization of defect generation in materials, in particular, in Si substrates during plasma processing. Some of the emerging topics - damage generation in three-dimensional structures and the recovery process - are discussed as future perspectives.