Parasitic bipolar gain reduction and the optimization of 0.25-/spl mu/m partially depleted SOI MOSFETs

An in-depth analysis of the role of parasitic bipolar gain reduction in 0.25-/spl mu/m partially depleted SOI MOSFETs is presented, considering both dc characteristics as well as circuit operation. The effect of channel doping, silicide proximity, and germanium implantation on the lateral bipolar gain are characterized for optimal performance and manufacturability. Channel doping has the expected impact on bipolar gain. Silicide proximity is shown also to have a large impact. Germanium implantation into the source/drain regions reduces the lateral bipolar gain due to the introduction of defects that act as recombination centers in the source, reducing emitter efficiency. Further, germanium implantation serves to finely control the silicidation process, leading to good manufacturing control of the lateral silicide encroachment. Analysis of MOSFET dc I-V characteristics shows that threshold voltages for SOI have to be set only 30-50 mV higher for comparable dc off current to bulk CMOS. Finally, the impact of bipolar gain on floating-body-induced hysteretic effects and on alpha-particle-induced SRAM soft error rates are described.